In the semiconductor integrated circuit (IC) industry, there is a continuing demand for higher circuit packing densities. This demand of increased packing densities has led the semiconductor industry to develop new materials and processes to achieve sub-micron device dimensions. Manufacturing ICs at such minute dimensions adds more complexity to circuits and increases the demand for improved methods to inspect integrated circuits in various stages of their manufacture.
As design rules and process windows continue to shrink, IC manufacturers face many challenges in achieving and maintaining yields and profitability while moving to new process technologies such as larger wafers, copper interconnect, and low-k dielectrics. Additionally, defects that were not relevant in the older, larger design rules have now become problems as design rules are reduced to 0.13 μm geometries and below.
Although inspection of such products at various stages of manufacture is very important and can significantly improve production yield and product reliability, the increased complexity of ICs increases the cost of such inspections, both in terms of expense and time. However, if a defect can be detected early in production, the cause of the defect can be determined and corrected before a significant number of defective ICs are manufactured.
In order to overcome the problems posed by defective ICs, IC manufacturers fabricate test structures. Such test structures are used in defect analysis. The test structures are fabricated such that they are sensitive to defects that occur in IC products, but are designed so that the presence of defects is more readily ascertained. Such defect test structures often are constructed on the same semiconductor substrate as the IC products.
Defect detecting systems frequently utilize charged particle beams. In such systems, a charged particle beam, such as an electron beam, is irradiated on defect test structures. The interaction of the electron beam with features in the circuitry generates a number of signals in varying intensities, such as secondary electrons, back-scattered electrons, x-rays, etc. Typically, electron beam methods employ secondary electron signals for the well known “voltage contrast” technique for circuit defect detection.
The voltage contrast technique operates on the basis that differences in the various locations of a test structure under examination cause differences in secondary electron emission intensities. In one form of inspection, the mismatched portion between the defective voltage contrast image and the defect free one reveals the defect location. Thus, the potential state of the scanned area is acquired as a voltage contrast image such that a low potential portion of, for example, a wiring pattern might be displayed as bright (intensity of the secondary electron emission is high) and a high potential portion might be displayed as dark (lower intensity secondary electron emission). Alternatively, the system may be configured such that a low potential portion might be displayed as dark and a high potential portion might be displayed as bright.
A secondary electron detector is used to measure the intensity of the secondary electron emission that originates only at a path swept by a scanning electron beam. A defective portion can be identified from the potential state of the portion under inspection. Semiconductor wafers are tested during manufacturing to ensure quality control. One way wafers can be tested is using an electron beam (e-beam) inspection tool, which detects, by way of irradiating a wafer with an electron beam, surface defects as well as so-called “voltage contrast defects” that can be caused by defects in layers underlying the surface layer. Such voltage contrast occurs as a result of differential charge build-up on features, such as metal landing pads. When negative charges accumulate on a feature, the resulting negative potential repels electrons, causing the feature to appear bright under an electron microscope. In contrast, a positive charge build-up causes the feature to appear dark. In this way, an e-beam tool can be used to derive, from the contrast of the return image, whether a defect such as an electrical short or open exists in the wafer. Thus, in such systems, the voltage contrast is simultaneously monitored for both defective and defect free circuits for each IC manufactured.
Test structures usually are designed and manufactured to comply with the design rules used to manufacture the IC, therefore as the geometry sizes in ICs are reduced test structures become very small thereby reducing the contrast in the area of defects under the influence of e-beam testing equipment. Consequently, it becomes very difficult to perform a review of the defects detected and any associated failure analysis.
Existing test structure design uses a vertical structure approach in which the same test structure is repeated vertically in every metal layer of the IC. This test structure design is difficult to implement as ICs use more layers of metal interconnect in higher density ICs.
Existing test structures also are designed to test for only one defect type, such as an open circuit or a short circuit, resulting in limited capability.
Existing test structures additionally occupy a large amount of space on a wafer making it difficult to incorporate the test structures into the IC products. In addition, existing test structures tend to introduce electrical noise and interference into the ICs being manufactured.
Solutions to these problems long have been sought but prior developments have not taught or suggested any solutions and, thus, solutions to these problems have long eluded those skilled in the art.